Many integrated circuits employ decoders, for example memories in which one address location is selected out of many based upon an input code. In order to implement such decoders it is necessary to provide an incoming signal A of one state and its complementary signal A of another state. Signals A and A may be generated externally of the integrated circuit and then brought into the decoder. However, this requires a large number of PINS and is very cumbersome.
A second method is to bring signal A into the package and then generate the complement A within the package by adding an inverter. This results in numerous fanning at the input loading of the package.
The preferred method is to bring the signal A into the package and then to double invert it with two inverters within the package, thus obtaining A from a first inverter and A, the complement of A and the equivalent of A, from a second inverter fed from the first inverter. This results in a large internal fan-in but the circuit packages are easily designed to handle this large internal fan-in. With such a dual inverter circuit it is desirable that, upon the input of the signal A, both internal inverters operate simultaneously to produce output signals A and A at the same instant in time. However, the series arrangement of the two inverters is such that the first inverter operates first in time to produce signal A, and the second inverter then responds to the operation of the first inverter to produce the complementary signal A. Since there is a slight delay between the response of the first inverter and that of the second inverter, there is a short period of time in which the outputs of the two inverters are in the same state rather than being complementary. When this delay is long enough, the decoder will react to the two similar states on the two inverter outputs to produce an undesired error in the state of one or more of the decoder outputs.
It has been suggested how the undesired delay time between operation of the first inverter and turn-on of the second inverter may be shortened by the circuit shown in FIG. 1 hereof and first disclosed in an article entitled, "Beware the Glitch" by Ury Priel on pages 43 and 44 of the section Design/Functions/Digital in EDN of Apr. 1, 1971.
In this circuit, the first inverter comprises input transistor Q1 and input resistor R1, phase splitter transistor Q2 and phase splitter resistor R2, turn off resistor R3, and the output stage comprising diode D1, pull down transistor Q3 and pull up resistor R4. The second inverter circuit comprises the phase splitter transistor Q4, turn off resistor R5, and the output stage including pull up resistor R6, diode D2, and pull down transistor Q5. In a more conventional dual inverter circuit, the drive for the base of phase splitter transistor Q4 would be obtained via another transistor Q6 from the collector of pull down transistor Q3. The output for A, and the turn on time of the second inverter would be delayed so that output A would be high along with output A for this delay time period .DELTA.t FIG. 2. In the circuit of FIG. 1, the drive for phase splitter transistor Q4 is taken at an earlier stage, i.e., at the collector of phase splitter transistor Q2, and the delay in turn-on time for the second inverter is substantially shortened. A primary drawback to the circuit of FIG. 1 is that the outputs A and A have resistive pull-ups, i.e., resistors R4 and R6, which reduce the speed of operation of the inverters when operating into a capacitive load; this is very undesirable in high speed circuits such as PROMs (Programmable Read Only Memories).